Counter anti-jitter circuit

ABSTRACT

A digital counter which incorporates a circuit to reduce or prevent jitter in output readings. During a time base signal, a fraction count circuit determines the fractional count of input signals. This fractional count information is combined with input signals prior to the time base signal by using a fractional count modifier circuit. The fractional count modifier circuit modifies the phase of the input signals prior to the start of the time base.

United States Patent Gra A r. 17, 1973 COUNTER ANTI-JITTER CIRCUIT 3,062,443 11/1962 Palmer "235/92 EA 2,521,788 9/l950 Grosdoff ..235/92 BD [75 1 Inventor Gray La Habra 3,551,809 12/1970 Dufour ..324/99 D Assignee; Laboratories Santa Ana D Calif. Primary ExaminerThomas A. Robinson [22] led: 1971 Assistant Examiner-Joseph M. Thesz, Jr. [21] APPL No; 199,976 Attorney-Charles G. Lyon et al.

' [57] ABSTRACT [52] US. Cl. .....235/92 PL, 235/92 EA, 235/92 DM,

23 5 /92 R, 324/99 D 340/324 R A digital counter which incorporates a circuit to 51 Int. Cl. ..H03k 21/34 H03k 21/02 reduce Prevent J'me readings- During a [58] Field of l 235/92 EA 92 PL time base signal, a fraction count circuit determines 235/92 1 92 DM92 the fractional count of input signals. This fractional IMO/3&4 R CC 324/99 count information is combined with input signals prior to the time base signal by using a fractional count [56] References Cited modifier circuit. The fractional count modifier circuit modifies the phase of the input signals prior to the UNITED STATES PATENTS start of the time base.

3,209,130 9/1965 Schmidt .235/92 PL aims, rawing lgures 16 Cl 10 D F' /0 3g g a 3d //\/PUT COUNT/N6 P66 Zy J 0/6/7741. 971/4 [1765 5,475 0/ W052 p /E 5756705 COO/V755 F66D5ACK CO/VTEOL z@ I w I l l 7/M6 5A 56 co/vreot COUNTER ANTI-.IITTER CIRCUIT BACKGROUND OF THE INVENTION The present invention relates to digital counters and the like and more particularly to an improved counter incorporating means for reducing or eliminating jitter in the readout thereof.

Conventional digital counters include an input shaping circuit, signal gate, time base, counting means and a control circuit as illustrated in FIG. 1 which will be described subsequently. Unless the length of the time base is an exact multiple of the period of the input frequency, it is possible for the counter to read either of two consecutive numbers on its visual readout representing the input frequency. The phase between the input frequency and the time base determines which of the two numbers will be contained in the counter at the conclusion of the time base. As a result of this operation, the numbers presented by the visual readout of the counter will vary between the two numbers giving the effect of jitter in the readout.

SUMMARY OF THE INVENTION Accordingly, it is a principal object of the present invention to provide an improved digital counter.

A further object of the invention is to provide a digital counter which has reduced jitter in the readout thereof.

An additional object of this invention is to provide in a digital counter a hysteresis characteristic which substantially reduces or eliminates jitter in the readout of the counter when counting input signals wherein a small amount of frequency modulation of the input signals may exist as a result of drift or noise.

A further object of this invention is to introduce a hysteresis characteristic into a digital counter for preventing jitter in the output readings thereof even though a small amount of frequency variation exists in the input signal.

BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and features of the present invention will become better understood through a consideration of the following description taken in conjunction with the drawings, in which:

FIG. 1 is a block diagram of the typical prior art digital counter;

FIG. 2 is a waveform diagram illustrating different phase relationships of input signals with the time phase of the counter of FIG. 1;

FIG. 3 is a block diagram of a preferred digital counter modified in accordance with the teachings of the present invention;

FIGS. 90 and 9b illustrate a detailed circuit diagram of a counter incorporating modifications according to the teachings of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Turning first to FIG. 1, the same illustrates a typical prior art digital counter including an input shaper 10,

FIG. 4 is a block diagram of an exemplary digital counting gate 11, time base and control circuit 12 further including a time base circuit 12a and a control circuit 12b, and a digital counter 13 with a visual digital readout 13a. As is known to. those skilled in the art, a counter of the nature shown in FIG. 1 functions to count input signals applied at an input 15 during the time base generated by the time base circuit 12a, an exemplary time base signal being shown at 18 in FIG. 2. In a typical counter, counting of the input signals at input 15 commences, for example when the time base goes positive at 18a, and counting terminates when the time base signal goes negative at 18b.

FIG. 2 illustrates the time base and two input signals applied to the input 15 which are of the same frequency but of different phases indicated as phase A and phase B with respect to the time base 18. As noted earlier, unless the length of the time base signal 18 is an exact multiple of the period of the input frequency, it is possible for the counter to read either of two consecutive numbers representing the input frequency. The phase between the input frequency and time base determines which of the two numbers will be contained in the counter at the termination 18b of the time base 18. This anomaly is illustrated in FIG. 2 wherein the input frequency having a phase A with respect to the time base 18 causes the counter to provide a readout of the number 5, and wherein an input frequency having a phase B with respect to the time base causes the counter to provide a readout of the number 4.

The amount of observable jitter on the readout 13a of the digital counter 13 depends on the relationship between the length of the time base 18 and the period of the input frequency. If the length of the time base is an exact multiple of the input frequency, there is no jitter as will be apparent to those skilled in the art. However, if the length of the time base is a multiple, plus a fraction, of the period of the input frequency, there is some jitter assuming that the input frequency is asynchronous with respect to the time base. If the fraction is one-half there is maximum jitter; that is, both numbers (such as, 5" and 4 in FIG. 2) appear with equal probability. For fractions less than, or more than, one-half, the jitter is less than the maximum, with one number having a higher probability of being read out than the other.

The usual time base circuit includes an oscillator followed by a counter to provide the output time base signal. One means proposed in the past for reducing the jitter is to control the start of the time base 18 so that the leading edge 18a is synchronized to some predetermined degree with the input frequency applied at input 15. This can be accomplished using one or more binary circuits or binaries between the oscillator and time base counter. These binaries are driven by the time base oscillator whose frequency has been increased by a factor equal to the division created by the addition of the binaries to the time base circuit, and results in the same frequency being applied from the oscillator to the time base counter. The advantage of using the binaries in this manner is that they may be reset with the first pulse of the input frequency. In this way the time base can be synchronized to the input frequency to within one period of the time base oscillator. The more binaries that are used, the higher the oscillator frequency, the shorter the oscillator period, and the better synchronized is the time base with the input frequency. In fact, the, phase, which would have a maximum value of a full input period without the synchronization, would be reduced to a maximum value of T l'l where T is the period of the time base oscillator and T is the period of the input frequency. However, even though the ration T lT may be small, there is a finite amount of jitter which increases as the input frequency becomes higher.

The concepts of the present invention enable substantial reduction or complete elimination of jitter in the readings of a digital counter. A further modification involves the addition of a. hysteresis characteristic which eliminates jitter in the presence of a small amount of frequencymodulation of the input signal which may be caused by drift or noise.

According .to the present concepts, two functionally related circuits, a fractional count modifier 24 and a fractional count detector 22 are added between the counting gate 11 and the digital counter 13 as shown in FIG. 3. Feedback from the second circuit to the first circuit is provided by a feedback control circuit 26. A

predivider 32 is an optional circuit that provides hysteresis to the readings when it is included. The fractional countdetector 22 contains an ending value during readout of the counter representing a fraction of a count associated with the reading. This value 'could be contained in one or more binaries or like digital means or in an analog means such as a ramp or other waveform generator with a holding amplifier or the like. The fractional count modifier 24 is capable of adding and/or subtracting a fraction of a count applied to the digital counter either prior to, during, or following the time base period. This may be accomplished with one or more binaries or like digital means or an analog means such as a ramp or other waveform generator with means for adding and/or subtracting energy in the reactive waveform-generating element. The fractional count modifier 24 is controlled by feedback information from the fractional count detector 22 through the feedback control means. Without the optional predivider circuit 32, jitter resulting from differing phase anglesbetween the input signal and the time base is reduced or eliminated. With the optional predivider 32 which contains one or more binary dividers orlike digital means or frequency dividing analog means, a hysteresis effect of readings versus direction of frequency change is introduced. Thishysteresis effect completely, eliminates reading jitter even when the input source contains a small amount of frequency modulation due to noise, drift, or the like.

FIG. 4 is an exemplary embodiment of a digital counter incorporating binaries B and A identified by reference numerals 24 and 22 representing the fractional count modifier and fractional count detector respectively. A reset gate 26 represents the feedback control and the optional predivider is not included.'

vide the input frequency applied to input 15 by four.

Since the fractional count detector 22 consists of binary A, the resolution of the detected fractional count is one-half. Since the fractional count modifier consists of binary B only which precedes binary A, the fractional count when added is one-fourth.

FIGS. 5 and 6 are waveforms which illustrate the operation of the circuit of FIG. 4 incorporating two additional binaries A and B. These figures illustrate a time base waveform 18. The output of binary B is illustrated at 28, and the output of binary A is illustrated at 29 in these figures. Assuming that the digital counter 13v counts a negative transition, as at 29a, from the output of binary A, at the end 18b of the time base signal 18 in FIG. 4, it will be seen that the binary A has an output that has just gone negative or low. This means that a count was added to the counter 13 just before the end 18b of the time base 18 and the fractional count is less than one-half. Assuming for the moment that the binary B and binary A circuits are reset to a low state at the beginning 18a of the time base 18, it will be apparent that if the phase d) between the time base 18 and binary B increases, the binary B and binary" A waveforms move or shift to the right with respect to the time base. Thus, it is possible for the time base to end (at 18b) beforebinary A makes its'last negative transition and the fractional count is greater than one-half. This would result in one less count in the counter 13, and jitter in the readings thereof.

Suppose, however, that binary B is reset to a that depends upon thefinal stateof binary A. In the example of FIG. 5, sincebinary A has just made a nega-? tive transition 29a before the end of the timebase 18 it would be desirable to reset binaryB to the state that would shift the binary A waveform to the left. This operation would insure, on the next reading, that the last negative transition 29a of binary A would occur sooner before the end of the time base 18. I I

As shown in FIG. 6, by resetting binary B to theopposite state, the binary A output waveform is shifted by one binary B input pulse to the left. This means that the phase it can increase to its limit of one input pulse period without losing the last negative transition 29:: of

binary A. Conversely, it can be seen that if binary A" ends in a high state, the waveform should be shifted to the right to insure no last transition or count even when the phase goes to zero. This can be accomplished b resetting binary B to its initially lowstate. 1

Accordingly, the exemplary ruleto be used according to the present concepts is to reset binary B to its initially high state if binary A is in its low state at the end of the time base, and to'reset binary B to its initially low state if binary A is in its high state at the end of the time base. This feedback control function. requires av minimum of two consecutive reset pulses. A first reset pulse resets binary B according to the status of binary A. A second reset pulse resets binary A and the digita counter 13.

Accordingly, the general rule to be used relating to the general concepts of FIG. 3 is to add a fraction of a state count to the next reading when the detected fraction of the ending count is less than one-half and to add nothing (or subtract a fraction of a count) when the detected fraction of the ending count is greater than onehalf.

6 FM tuner applications wherein a hysteresis characteristic is introduced that prevents jitter in the readings even though small amount of frequency jitter exists on the input signal being counted. This is accomplished by 5 introducing a predivider which might consist of one or FIG. 7 shows that as an alternative, the output lines more binary circuits preceding binary B, such as binary from the feedback control circuit 26 can, instead of C identified by reference numeral 32 in FIG. 6. The efgoing to the fractional count modifier 24, be applied to fect of adding binary C is to restrict the phase d) to a the first stage or stages of the time base circuit 12a used maximum of one fourth Of a binary B period. The in the time base and control circuit 12. The first stage anlonm of hysteresis effect 15 q l to one'fouljth of 3 or stages become in essence a fractional count modifier 'f 'y B Perlod which equals e of a h y A f the time base counter and may use the Same or period, or one-eighth of a count. This means, in effect, similar circuits. A typical example would be one binary that If the Input frequency gradually Increased 5 reset to one state or the other depending on the output when tuning a tuner) h a new heading just appears of fractional count detector 22 as applied through the 15 oh the counter 1t h then he h e by a feedback control 26.The general rule is to lengthen the frequency eqhat to ehe'elghth eehht thvlded by the time base when the detected fraction of the ending total pehod of h base 18 In order to ebtalh or read count is less than onehalf and to shorten the time base the te reathhghh the readout of the counter when the detected fraction of the ending count is 20 e Adthttehat blhaheshlse can he added to the greater than one-half. Modifying the time base results when l q as l t bmatges g added 2: hystetests in an amount of shift which is a constant time period :P e f b 'ls l l a rather than a fraction of the input signal period, but matlons 0 memes can 6 emp eye as we as l e ferent feedback arrangements. nonetheless serves to reduce or eliminate the itter m the readings In FIG. 4, two binaries A and B are used with feedback by line 25 from the output of binary A to binary B. The improved counter circuit shown in FIG. 4 mcor- With only these two binaries there 18 no hysteresis efporatlng the antiitter feature results in no itter profect because the change in counter reading occurs at vided that the input frequency IS constant and without the same frequency for increasing frequency or any frequency modulation components. However, if d f 1 h h h the in ut fre uenc (or time base oscillator) jitters echeasme e h he ls ts w et er t outpllt h f q y b b of binary A IS initially reset high or low with a dif- S lg m requency some Imelm the mg may e o ference of two input cycles involved since it takes two Serve input cycles to change the state of binary A. The are peteht'al for h shghthttet m teadlhgs may be rangement of FIG. 8 is essentially the same as that of exphhhee by eehstdenhg thpht frequency that FIG. 4 with feedback from the output of binary A to bie e the t hegath'e ttahstheh of emery A to nary B, but with the addition of binary C as a predivider Just hethg Counted at the end 18b of h tlme base and application of input signals to binary C rather than when e Phase 15 equal to zero: That as Shown binary B. This results, as noted above, in a hysteresis ef- In 5 wlth the end of the thnary waveform fect of one-eighth of a count. On the other hand, if the 29 to the l the Shght amount f e to Include the 40 binary C is used as shown in FIG. 8, but the feedback last negative transition 29a within the time base, bmary from the output of binary A is applied to binary C B be reset to its high State, n hlnary A wlh then rather than to binary B, no hysteresis effect is realized, be Shifted l binary B Penod left- T since a predivider no longer exists. Binary B becomes PhaSe 4 y now Increase to W binary B Penod functionally an inactive part of the fractional count to P the bmary A final transition at the end of the modifier circuit. Different arrangements of this nature time base where a small amount of frequency drift of illustrated i Table 1 below wherein; noise could shift this final transition beyond the end of N number f input cycles into the fi t binary (Len the time base. Binary B would then be reset to its lowest B,C, or 1)) d i th i b i d, state where it would remain until the phase 11) went to R digital counter reading for any number N of zero and noise caused the cycle to repeat. input cycles.

The result of this latter yp Operation is a slight INT means the integral part of the value in parentheamount of jitter in the readings if the input frequency is i on the borderline between two adjacent readings and The arrows between A and B or C in the tabl bel w slightly noisy. This jitter may be eliminated for small are illustrative of the feedback between the binaries amounts of noise if is restricted to less than one-half a noted earlier. Although not necessary, all binaries exbinary B period. f h b d f cept A and the one receiving the feedback as indicated Accordingly, FIG. 8 depicts a urt er em 0 iment o by the arrow head are assumed reset to their low state the resent conce ts which is articularl useful for in this illustration.

P P P y TABLE I a P. r "-r\ A, reset Frequency B A C B A (3 ii A I) C B A l) C I! A N+3 pjfs g-t N+n N+u High Increas1ng.. RINT( R-II\T( 8 R-]NT( 8 R-INT( 16 R 1NT(- N+3 'is A N+5 N+12 N+10 Do Decreaslngun R=INT(T) R-INI( 8 R-LNT( R lNr( R-II\T(-16 c Efl li 1 L0 Inc1eas1ng R-INT 4 R1NT 8 RINT( 8 RII\T 16 RINT( 16 N+1 N+2 N+1 N+4 t: L0 Docreasing R=iNT( R-INT(8) R-INT(-8) R-INT( 16 R-INT 16 It will be seen from columns Nos. 2, 4 and 5 that a hysteresis efiect is achieved by adding one or more binaries preceding the binary receiving thefeedback. The arrangement depicted in column 2 is the arrangement of FIG. 8 and the hysteresis is one-eighth count. The one-eighth count difference is between frequency increasing" and decreasing as can be seen from the term N+5/8 as compared to N+6l8 in the first and second rows of the table, or the term N+l/8 as compared to N+2/8 in the third and fourth rows. The arrangement of column No. 4 results in a hysteresis effect of three-sixteenths count and the arrangement of column No. 5 in one-sixteenth of a count. On the other hand, the arrangements illustrated in column Nos. 1 and 3 result in no such hysteresis effect (column 1 depicts the arrangement of FIG. 4). As the number of prior binaries (e.g., C, D, and so forth) are increased,

the hysteresis effect approaches a limit of one-fourth tive half cycle. This arrangement eliminates the necessity of additional storage elements. The line sync circuit 61 serves to sync the reset signals with the negative half cycle of the power supply'input.

The time base and control circuit 63 includes a crystal oscillator 64 as illustrated in the lower left hand comer of FIG. 9a. The circuit 63 also includes decade counting units 66 through 68. The time base signal is applied von an output line 70, and enables the binary C to count. Although not required, the time base signal also enables B. Suitable reset signals are applied on output lines 71-73 of the circuit 63. The reset signals on these lines occur at slightly different times. The main criteria is to place binary B 45 in its correct initial state before the counter 47-49 is reset since resetting destroys the binary A ending state information in the first stage of the counting unit 47 l bit). The reset t t t l I plying information to said fractional count modifier means.

2. A digital counter as in claim 1 wherein said fractional count modifier means and fractional count detector means include first and second binary circuits connected between said input circuit means and the input of the said digital counting means, and said feedback control means is coupled between the output of said second binary cirlo cuit and said first binary circuit to control the state of said first binary circuit as a function of the state of the second binary circuit.

3. A digital counter as in claim 1 wherein said fractional count modifier means and fractional count detector means include first and second binary circuits connected between said input circuit means and the input of the said digital counting means, and said feedback control means is coupled between the output of said second binary circuit and said first binary circuit to control the state of said first binary circuit as a function of the state of the second binary circuit at the end of the time base signal provided by said time base and control means.

4. A digital counter as in claim 2 including an additional binary circuit interposed between said input circuit means and said first binary circuit.

5. A digital counter as in claim 4 wherein said time base and control means resets said additional binary circuit upon reset of said second binary circuit and said digital counting means.

6. A digital counter as in claim 1 wherein said fractional count modifier means and said fractional count detector means comprise first and second binary circuits connected between said input circuit means and the input of said digital counting means, and said feedback control means comprises gate means coupled to receive signals from said second binary circuit and to apply control signals to said first binary circuit to (a) cause said first binary circuit to assume a first state if said binary circuit is in a second state at the end of the time base signal provided by said time base and control means, and (b) cause said first binary circuit to assume a second state if said second binary circuit is in a first state at the end of said time base signal.

7. A digital counter as in claim 1 wherein said fractional count modifier means and said fractional count detector means comprise first and second binary circuits coupled with said digital counting means, and

said time base and control means provides first and second reset pulses with a first reset pulse being applied to reset said first binary circuit according to the state of said second binary circuit, and a second reset pulse being applied to reset said second binary circuit and said digital counting means.

8. A digital counter as in claim 6 wherein said time base and control means provides first and second reset pulses with the first reset pulse being applied to reset said first binary circuit according to the state of said second binary circuit, and a second reset pulse being applied to reset said second binary circuit and said digital counting means.

9. A digital counter as in claim 1 including first binary circuit means forming a predivider for providing a hysteresis effect, said fractional count modifier means and said fractional count detector means including second and third binary circuits connected between said first binary circuit means and the input of said digital counting means, said input circuit means being coupled to said first binary circuit means, and

means coupled with said third binary circuit for sampling the state thereof at a predetermined portion of a time base signal provided by said time base and control means and for causing said second binary circuit to assume a state as a function of said state of said third binary circuit.

10. A digital counter as in claim 1 wherein said time base and control means includes a time base counter having binary means for forming said fractional count modifier means.

1 1. A digital counter characterized by stability in the visual readout thereof in the presence of slight frequency variations in input signals applied to said counter, comprising digital counting means for counting phase modified signals representative of input signals applied thereto over a time base period and providing a visual readout thereof,

time base and control means for providing a time' base signal independent of the input signals and controlling the application of said phase modified signals to said digital counting means,

three binary circuit means preceding the input of said digital counting means for receiving input signals to be counted and for applying phase modified signals to said digital counting means, said first binary circuit means detecting the value of a fractional count occuring during a time base period, said second binary circuit means combining the fractional count of said first binary circuit means with the input signals, thereby modifying the phase of the input signals prior to the start of the time base period, and

gate means responsive to the state of the third of said binary circuit means at a predetermined portion of said time base signal and connected to the second of said binary circuit means for allowing said second binary circuit means to assume a state which is a function of said state of said third binary circuit means.

12. A counter as in claim 11 wherein said time base and control means resets said first binary circuit means upon reset of said third binary circuit means and said digital counting means after said second binary circuit means has assumed said state.

13. A method of reducing jitter in the visual readout of a digital counter, said counter comprising digital counting means for counting input signals applied thereto and providing a visual readout thereof, time base control means for providing a time base signal, independent of the input signals, over which input signals to said counting means are to be counted, and binary circuit means for prescaling input signals to said counting means, said binary circuit means including at least first and second binary circuits, said second binary circuit detecting the value of a fractional count as the conclusion of the time base signal, and said first binary circuit modifying the phase of the input signals in response to the state of said second binary circuit, said first and second binary circuits controlled according to the steps of causing said first binary circuit to assume a first state if the second binary circuit is in a second state at the end of said time base signal, and causing said first binary circuit to assume a second state if the second binary circuit is in a first state at the end of said time base signal. 14. A method as in claim 13 including the step of additional predividing input signals to be counted before application thereof to said first binary circuit. 15. A method of reducing the jitter in the visual readout of a digital counter having digital counting means for counting input signals applied thereto and providing a visual readout thereof, time base means for providing a time base signal, independent of the input signals, over which input signals to said digital counter as are counted by said counting means, and binary circuit means for prescaling the input signals applied to said counting means, comprising the steps of sensing the state of said binary circuit means, said state of said binary circuit means being representative of the fractional count at the conclusion of the time base signal, and

controlling the phase relationship between said time base signal and output signals from said binary circuit means to the input of said counting means as a predetermined fiiiiciitii'of' the state of said binary circuit means during a portion of a preceding time base signal.

16. A digital counter characterized by reduced jitter in the output thereof comprising input circuit means for receiving input signals to be counted, and for producing first signals representative of the input signals,

digital counting means for counting phase modified signals applied thereto over a given time base period and providing a readout thereof,

time base and control means for providing a time base signal, independent of the input signals and for applying the phase modified signals to said digital counting means, said time base and control means including fractional count modifier means for modifying the phase of the first signals prior to the state of the time base signal,

fractional count detector means coupled with said digital counting means for detecting the value of a fractional count occurring during the time base period of said time base and control means, said fractional count modifier means modifying the phase of the first signal in response to the value of the fractional count of said fractional count detector means, and feedback control means for accepting information from said fractional count detector means and applying information to said fractional count modifier means. 

1. A digital counter characterized by reduced jitter in the output thereof comprising input circuit means for receiving input signals to be counted, and for producing first signals representative of the input signals, digital counting means for counting phase modified signals applied thereto over a given time base period and providing a readout thereof, time base and control means for providing a time base signal, independent of the input signals and for applying the phase modified signals to said digital counting means, fractional count detector means coupled with said digital counting means for receiving the first signals from said input circuit means and for detecting the value of a fractional count occurring during the time base period of said time base and control means, fractional count modifier means for combining the fractional count from said fractional count detector means with the first signals from said input circuit means, and for modifying the phase of the first signal prior to the start of the time base signal, thereby forming phase modified signals, and feedback control means for accepting information from said fractional count detector means and applying information to said fractional count modifier means.
 2. A digital counter as in claim 1 wherein said fractional count modifier means and fractional count detector means include first and second binary circuits connected between said input circuit means and the input of the said digital counting means, and said feedback control means is coupled between the output of said second binary circuit and said first binary circuit to control the state of said first binary circuit as a function of the state of the second binary circuit.
 3. A digital counter as in claim 1 wherein said fractional count modifier means and fractional count detector means include first and second binary circuits connected between said input circuit means and the input of the said digital counting means, and said feedback control means is coupled between the output of said second binary circuit and said first binary circuit to control the state of said first binary circuit as a function of the state of the second binary circuit at the end of the time base signal provided by said time base and control means.
 4. A digital counter as in claim 2 including an additional binary circuit interposed between said input circuit means and said first binary circuit.
 5. A digital counter as in claim 4 wherein said time base and control means resets said additional binary circuit upon reset of said second binary circuit and said digital counting means.
 6. A digital counter as in claim 1 wherein said fractional count modifier means and said fractional count detector means comprise first and second binary circuits connected between said input circuit means and the input of said digital counting means, and said feedback control means comprises gate means coupled to receive signals from said second binary circuit and to apply control signals to said first binary circuit to (a) cause said first binary circuit to assume a first state if said binary circuit is in a second state at the end of the time base signal provided by said time base and control means, and (b) cause said first binary circuit to assume a second state if said second binary circuit is in a first state at the end of said time base signal.
 7. A digital counter as in claim 1 wherein said fractional count modifier means and said fractional count detector means comprise first and second binary circuits coupled with said digital counting means, and said time base and control means provides first and second reset pulses with a first reset pulse being applied to reset said first binary circuit according to the state of said second binary circuit, and a second reset pulse being applied to reset said second binary circuit and said digital counting means.
 8. A digital counter as in claim 6 wherein said time base and control means provides first and second reset pulses with the first reset pulse being applied to reset said first binary circuit according to the state of said second binary circuit, and a second reset pulse being applied to reset said second binary circuit and said digital counting means.
 9. A digital counter as in claim 1 including first binary circuit means forming a predivider for providing a hysteresis effect, said fractional count modifier means and said fractional count detector means including second and third binary circuits connected between said first binary circuit means and the input of said digital counting means, said input circuit means being coupled to said first binary circuit means, and means coupled with said third binary circuit for sampling the state thereof at a predetermined portion of a time base signal provided by said time base and control means and for causing said second binary circuit to assume a state as a function of said state of said third binary circuit.
 10. A digital counter as in claim 1 wherein said time base and control means includes a time base counter having binary means for forming said fractional count modifier means.
 11. A digital counter characterized by stability in the visual readout thereof in the presence of slight freQuency variations in input signals applied to said counter, comprising digital counting means for counting phase modified signals representative of input signals applied thereto over a time base period and providing a visual readout thereof, time base and control means for providing a time base signal independent of the input signals and controlling the application of said phase modified signals to said digital counting means, three binary circuit means preceding the input of said digital counting means for receiving input signals to be counted and for applying phase modified signals to said digital counting means, said first binary circuit means detecting the value of a fractional count occuring during a time base period, said second binary circuit means combining the fractional count of said first binary circuit means with the input signals, thereby modifying the phase of the input signals prior to the start of the time base period, and gate means responsive to the state of the third of said binary circuit means at a predetermined portion of said time base signal and connected to the second of said binary circuit means for allowing said second binary circuit means to assume a state which is a function of said state of said third binary circuit means.
 12. A counter as in claim 11 wherein said time base and control means resets said first binary circuit means upon reset of said third binary circuit means and said digital counting means after said second binary circuit means has assumed said state.
 13. A method of reducing jitter in the visual readout of a digital counter, said counter comprising digital counting means for counting input signals applied thereto and providing a visual readout thereof, time base control means for providing a time base signal, independent of the input signals, over which input signals to said counting means are to be counted, and binary circuit means for prescaling input signals to said counting means, said binary circuit means including at least first and second binary circuits, said second binary circuit detecting the value of a fractional count as the conclusion of the time base signal, and said first binary circuit modifying the phase of the input signals in response to the state of said second binary circuit, said first and second binary circuits controlled according to the steps of causing said first binary circuit to assume a first state if the second binary circuit is in a second state at the end of said time base signal, and causing said first binary circuit to assume a second state if the second binary circuit is in a first state at the end of said time base signal.
 14. A method as in claim 13 including the step of additional predividing input signals to be counted before application thereof to said first binary circuit.
 15. A method of reducing the jitter in the visual readout of a digital counter having digital counting means for counting input signals applied thereto and providing a visual readout thereof, time base means for providing a time base signal, independent of the input signals, over which input signals to said digital counter as are counted by said counting means, and binary circuit means for prescaling the input signals applied to said counting means, comprising the steps of sensing the state of said binary circuit means, said state of said binary circuit means being representative of the fractional count at the conclusion of the time base signal, and controlling the phase relationship between said time base signal and output signals from said binary circuit means to the input of said counting means as a predetermined function of the state of said binary circuit means during a portion of a preceding time base signal.
 16. A digital counter characterized by reduced jitter in the output thereof comprising input circuit means for receiving input signals to be counted, and for producing first signals representative of the input signals, dIgital counting means for counting phase modified signals applied thereto over a given time base period and providing a readout thereof, time base and control means for providing a time base signal, independent of the input signals and for applying the phase modified signals to said digital counting means, said time base and control means including fractional count modifier means for modifying the phase of the first signals prior to the state of the time base signal, fractional count detector means coupled with said digital counting means for detecting the value of a fractional count occurring during the time base period of said time base and control means, said fractional count modifier means modifying the phase of the first signal in response to the value of the fractional count of said fractional count detector means, and feedback control means for accepting information from said fractional count detector means and applying information to said fractional count modifier means. 